1. The Field of the Invention
The present invention relates to methods of patterning a volume of silicon-containing material on a semiconductor substrate. More particularly, the present invention relates to methods of forming shaped structures from a volume of silicon-containing material on a semiconductor substrate using ion implantation and an etching process which is selective to either implanted silicon-containing material or to unimplanted silicon-containing material. The present invention is particularly useful for forming shaped silicon-containing material structures such as polysilicon plugs, interconnect lines, transistor gates, trenches, and capacitor storage nodes in an efficient manner and with a high degree of control over the resulting profile of the shaped structure.
2. The Relevant Technology
In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above.
Integrated circuits on electronic chips provide the logic and memory of computers and other intelligent electronic devices. These integrated circuits have advanced to a highly functional level to the benefit of the computers and other intelligent electronic devices. The vast functionality of integrated circuits is also being provided at a cost that is economical, allowing the computers and intelligent electronic devices to be provided to consumers at affordable prices. Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. The conventional semiconductor devices which are formed on the semiconductor wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor wafer.
The computer and electronics industry is constantly under market demand to increase the speed and functionality and to reduce the cost of integrated circuits. One manner of accomplishing this task is by increasing the density with which the semiconductor devices can be formed on a given surface area of a semiconductor wafer. In order to do so, the semiconductor devices must be decreased in dimension in a process known as miniaturization. The challenge in miniaturizing integrated circuits is to do so without greatly increasing the cost of the processes by which integrated circuits are manufactured.
Accordingly, one aspect of integrated circuit manufacturing that is in need of improvement is the complexity of the processes by which integrated circuits are manufactured. As integrated circuits have become increasingly complex, processing steps for forming the integrated circuits have multiplied in length. The number of fabrication process steps has also increased in proportion to the increased complexity of the integrated circuits. It is axiomatic that, as integrated circuit manufacturing processes increase in complexity, the cost of production of the integrated circuits correspondingly increases. Accordingly, in order to maintain an affordable cost of production of the improved and more functional computers and other intelligent electronic devices, new methods for manufacturing integrated circuits are needed which are simpler and more efficient, which assist in the miniaturization process, and which do not compromise integrated circuit quality or performance.
One necessary stage of conventional integrated circuit manufacturing processes is the formation of shaped structures which are used to form the semiconductor devices or discrete features of the semiconductor devices, such as MOS transistor gate regions and capacitor storage nodes. These shaped structures are generally formed by the patterning of structural layers on the semiconductor wafer. The structural layers are typically patterned with a process which includes depositing the structural layer, covering the structural layer with a photoresist mask, and etching away portions of the structural layer that are not covered by the photoresist mask. The portion or portions of the structural layer that are covered by the photoresist mask form the shaped structure.
The photoresist mask through which the structural layer is etched is conventionally formed by a process known as photolithography. Photolithography generally utilizes a beam of light, such as ultraviolet (UV) light, to transfer a pattern through an imaging lens from a photolithographic template to a photoresist coating which has been applied to the structural layer being patterned. The pattern of the photolithographic template includes opaque and transparent regions with selected shapes that match corresponding openings and intact portions intended to be formed into the photoresist coating. The photolithographic template is conventionally designed by computer assisted drafting and is of a much larger size than the section of the semiconductor wafer on which the photoresist coating is to be exposed. Light is passed through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the required size on the wafer. For positive photoresist the portions of the photoresist coating that are unmasked are developed away.
The resolution with which a pattern can be transferred to the photoresist coating from the photolithographic template place limits upon feature sizes that can be created. The dimensions of the openings and intact regions of the photoresist mask, and consequently the dimensions of the shaped structures that are formed with the use of the photoresist mask, are correspondingly limited. Photolithographic resolution limits are thus a barrier to further miniaturization of integrated circuits. Accordingly, a need exists for an improved method of forming shaped structures having feature sizes smaller than 0.2 microns.
As an example of one such shaped structure which is in need of being formed with reduced size is an ovonic cell of a programmable resistor. An ovonic cell is a region of chalcogenide material that has a resistance which is programmable by an electrical charge passed through the ovonic cell. Generally, the ovonic cell is formed by etching out an opening from a volume of material, and thereafter depositing the chalcogenide material into the opening. As a high charge density is most suitable for programming the ovonic cell, it is desirable that the opening be formed with a small cross-sectional area, which serves to increase the density of a charge applied thereto. The opening is conventionally patterned with photolithography. It would be desirable to find a commercially feasible method of forming the opening with a width narrower than about 0.2 microns.
Certain alternative methods to photolithography for forming shaped structures of semiconductor devices with higher resolution than is possible with photolithography do currently exist, but these alternative methods have certain drawbacks and limitations which keep them from being widely employed. For example, one such alternative method is referred to as a disposable spacer flow process. The disposable spacer flow process involves initially forming a sacrificial block of material and then forming spacers at the edges of the sacrificial block of material. The sacrificial block of material is situated such that the spacers are formed in the locations where resulting high resolution shaped structures are to be located. Once the spacers are formed, the sacrificial block of material is removed and the spacers remain to form the shaped structures. As photolithography is not used in forming the spacers, the spacers are not restricted by current photolithography resolution limitations, and can be formed with dimensions less than or equal to 0.2 microns.
One problem with the disposable spacer flow process, however, is that it is limited in the types of shaped structures that can be formed thereby. Generally, such shaped structures must be of a single width. That is, when a sub-photolithography feature, such as an interconnect line, is formed with the disposable spacer flow process at a sub-photolithographic resolution width, the entire interconnect line must be of sub-photolithographic resolution width. The interconnect line cannot then be connected with structures of greater size without further deposition and masking steps to form wider portions of the interconnect lines to which the wider structures can be connected.
There is a need currently existing in the art for a method whereby a shaped structure, such as a semiconductor device feature, can be formed in a manner which is simpler and more efficient than current existing process flows. From the prior discussion, it is apparent that such a method would be additionally beneficial if it could be used to form the shaped structure with reduced dimensions from those that can be achieved with conventional photolithography and in a manner that is more flexible than photolithography-alternatives such as the disposable spacer flow.
Etching processes that selectively etch insulating surfaces efficiently are common. Less common are etching processes that etch conducting layers efficiently and with flexibility. One type of structural layer that is frequently used in forming shaped structures, and particularly shaped structures that are conductive to electricity, is polysilicon. Polysilicon is frequently used in integrated circuit formation and is preferred, in part, because it is easily deposited. Deposition of polysilicon is typically conducted with the use of chemical vapor deposition (CVD) which is typically conducted in a deposition chamber with a chemical reaction involving the pyrolitic decomposition of a precursor material such as silane, disilane, or dichlorosilane.
In order to form a shaped structure from polysilicon, the polysilicon is deposited as a structural layer and is then patterned. Patterning of a layer of polysilicon is conventionally accomplished with a process that involves photoresist patterning and thus the above-discussed shortcomings attendant thereto. Conventional processes for patterning polysilicon also generally involve dry etching with a plasma etching process, which also has certain shortcomings that will be discussed below.
Generally, when etching to form a shaped structure, it is desirable to be able to etch orthogonally into the material being etched. Such an etching process is referred to as an anisotropic etching process. Anisotropic dry etching is a form of etching in which the semiconductor wafer is bombarded with ions generated by a plasma that is formed in a flow of one or more etchant gases. Typically, one or more halocarbons and/or one or more other halogenated compounds are used as the etchant gas. For example, CF4, CHF3 (Freon 23), SF6, NF3, and other gases are conventionally used as the etchant gas. Additionally, gases such as O2, Ar, N2, and others are also added to the gas flow. The particular gas mixture used depends on, for example, the characteristics of the material being etched, the stage of processing, the type of etching system being used, and the desired etch characteristics, such as etch rate and degree of anisotropy.
The anisotropic nature of dry etching is desirable, but it has the drawback of not being highly selective to different types of layers. Because of this drawback, it is difficult to precisely terminate a dry etching process at a desired depth to form a shaped structure with a sharp profile. Also, the patterns that can be formed with a single photoresist masking and dry etching step are limited to a single depth, and to the patterns that can be formed with photoresist. Consequently, forming a shaped structure having a complicated profile requires multiple repeated masking and dry etching steps, which drives up cost. Therefore, it is desirable to design a more controllable etching process, capable of patterning a structural layer such as a polysilicon layer anisotropically, yet with greater control of feature size and profile, and at a low cost.
Such an improved method would also provide numerous collateral advantages in addition to those discussed above. For instance, in order to increase the functionality of the integrated circuit, it would be beneficial if an improved method could be provided that imparts a flexibility to the types of profiles of the shaped structures that can be formed thereby. It would also be beneficial if the improved method simplified the process flows of certain semiconductor device formation processes in order to meet the demand for reduced cost discussed above. In order to further illustrate these and other needs of integrated circuit manufacturing processes, several representative conventional process flows and their limitations will be discussed herein.
A first representative example of a process flow in need of improvement is discussed below. In particular, it is necessary at several stages during an integrated circuit manufacturing process to form openings in an insulative layer of material. Conductive material is deposited into the openings in order to make electrical contact to underlying semiconductor devices or discrete features of semiconductor devices. Generally, an opening through an insulating layer exposing an active region is referred to as a contact opening, while an opening through an interlevel dielectric layer is referred to as a via opening. The term interconnect structure opening will be used herein to collectively refer to such openings through an insulative layer. Contact openings and via openings are filled with a conductive material to form a contact or via. A contact or via opening filled with polysilicon is generally referred to as a polysilicon plug. As used herein, the term interconnect structure will be used to collectively refer to conductive structures such as contacts, vias, and plugs that electrically connect discrete semiconductor device features located on differing levels of a semiconductor wafer.
To form an interconnect structure opening or another such opening through an insulating layer under conventional process flows, a photoresist mask is formed over the insulating layer and is patterned to leave exposed the area above the location of the insulating layer where the interconnect structure opening is intended to be formed. Material is then removed from the insulative layer to form the opening with an etching process which, in current conventional process flows, is typically the dry etching process discussed above.
The dry etching process has proven problematic, as discussed above, due to its lack of selectivity to different types of materials. In forming interconnect structures with a high density, high aspect ratio interconnect structure openings are required. The aspect ratio of an opening, as used herein, refers to the ratio of the primary vertical dimension of the opening divided by the primary horizontal dimension of the opening. Forming interconnect structures with a high aspect ratio requires a high selectivity of the etching process so that the etching process does not over etch, such as into an underlying silicon substrate. A measure of selectivity is typically achieved with the use of a silicon nitride etch barrier layer. Nevertheless, as aspect ratios increase, it is increasingly difficult to consistently form interconnect structure openings with high aspect ratios using conventional dry etching processes.
Conventional dry etching processes also exhibit poor uniformity, as it is difficult to uniformly etch the entire wafer surface with conventional dry etching processes. Yet another problem associated with dry etching is that it is difficult to dry etch surfaces which are not smooth and have a nonuniform topography. When dry etching such interconnect structure openings, uniformity problems occur in which open surfaces are etched faster than recessed surfaces, and in which the selectivity of the dry etching process varies for the depth of the feature being etched. Thus, a high selectivity is difficult to maintain in surfaces with a nonuniform topography.
A further limiting factor in interconnect structure opening formation is the difficulty involved in masking prior to etching interconnect structure openings. The mask is formed with openings for the interconnect structures that are extremely small when forming high density contact openings, which makes it difficult to correctly align the mask openings to the proper locations on the semiconductor substrate.
To complete an interconnect structure once the interconnect structure opening is formed, the interconnect structure opening is filled with a metal such as aluminum or tungsten. Filling the interconnect structure opening with metal causes additional problems, however, in that aluminum and tungsten do not form a highly conductive interface with an underlying epitaxial silicon of an active region. Aluminum diffuses into the active region and can form conductive spikes that short out the active region. Tungsten tends to chemically react and leave voids at the active region that reduce the conductivity of the interconnect structure. Consequently, when using the aluminum or tungsten as filler materials, elaborate steps of forming a liner layer must be conducted. Formation of the liner layer also poses difficulty, however, as the deposition of the liner layer tends to narrow the contact opening, making it difficult to effectively deposit the filler material.
One type of interconnect structure used to overcome the problems associated with filling the interconnect structure opening is the polysilicon plug. To form a polysilicon plug, an insulating layer is first formed over a semiconductor device feature which is to be provided with electrical communication by the polysilicon plug. The semiconductor device feature typically comprises an active region of a transistor. In MOS transistors, the active region is a source/drain region. Once the active region is formed, an insulating layer such as borophosphosilicate glass (BPSG) is subsequently formed, and is then reflowed. A contact opening is then etched through the insulating layer using photolithography and dry etching. The contact opening is subsequently filled with polysilicon. The polysilicon is typically deposited by chemical vapor deposition as a blanket layer of polysilicon over the entire insulating layer. The portion of the blanket polysilicon layer extending above the insulating layer is then removed using a planarization process such as CMP or a dry etch. Alternatively, the portion of the polysilicon layer situated above the polysilicon plug can be removed by masking the polysilicon and etching the remainder of the polysilicon layer away.
Polysilicon plugs are advantageous in that they form a highly conductive interface to the underlying crystalline silicon of the active region, which thereby overcomes the diffusion problems of interconnect structure formation processes that use metals for the conductive filing material. On the other hand, polysilicon plugs are problematic in that the dry etching process discussed above must still be conducted in the formation of the interconnect structure opening in which the polysilicon plug is formed. Conventional polysilicon plug formation processes are complex. Such complexity restricts throughput and increases the opportunity for error, thereby driving up integrated circuit fabrication costs. Consequently, a need also exists for a method whereby interconnect structures, and especially polysilicon plugs for high aspect ratio interconnect openings, can be formed efficiently and simply and without the need for dry etching to form a high aspect ratio interconnect structure opening.
A further shaped structure which is frequently formed in integrated circuit manufacturing is the capacitor. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. The storage node and cell plate are frequently formed from polysilicon. The polysilicon of the storage node and the cell plate are generally deposited separately and are patterned by conventional photolithography and dry etching. An intervening dielectric layer is formed between the formation of the storage node and the cell plate, typically by growth of silicon dioxide through exposure to oxygen.
An important consideration of forming capacitors in integrated circuits is surface area. A larger surface area of the storage node and upper capacitor cell plate provides greater capacitance. Balanced against this need is the competing requirement that the capacitor occupy a minimum of space on the silicon substrate of the semiconductor wafer. One manner in which the prior art has approached capacitor formation in order to obtain a greater surface area without increasing the space occupied on the silicon substrate is to form the capacitor at a distance above the silicon substrate. When so doing, one of the storage node and the cell plate are typically wrapped around the other in a compact area, forming what is known as a stacked capacitor. One problem common with the various configurations of stacked capacitors and the processes used to form them is that the processes are generally complicated and lengthy, increasing the opportunities for defect conditions to occur and driving up cost. Consequently, a method is needed for forming a stacked capacitor with a large surface area yet occupying a minimum of space on the silicon substrate in a simple and efficient manner. It is also desirable to gain greater charge storage area by integrally forming the stacked capacitor storage node and the underlying interconnect structure.
An additional problem attendant to forming a stacked capacitor is that the stacked capacitor must be linked in electrical communication to an active region on the silicon substrate underlying the capacitor storage node. It is critical in maintaining a high speed of the integrated circuit that the stacked capacitor maintain a high rate of charge retention. This is particularly so in forming integrated circuits that provide memory functions, such as dynamically refreshable random access memory (DRAM) integrated circuits. In order to maintain a high charge retention in the storage node, the stacked capacitor is generally separated from the silicon substrate.
Forming an interconnect structure from an active region on a silicon substrate to a stacked capacitor, however, poses certain difficulties. For instance, conventional methods of forming interconnect structures electrically connecting the storage node with the underlying active region typically involve forming an interconnect structure opening of an extended depth and then filling the interconnect structure opening, typically with polysilicon. The processes which do so, however, are difficult to conduct, as they have narrow process windows for correctly controlling all process parameters such that a defect condition does not occur. For instance, an interconnect structure opening with an aspect ratio of over two to one may be difficult to accomplish with standard dry etching processes.
A further semiconductor device for which an improved manufacturing process is needed is the MOS transistor. The transistor is the mainstay of modem integrated circuit fabrication, and integrated circuits such as microprocessors often utilize millions of transistors in a single chip. Currently, the MOS transistor is the most common type of transistor in integrated circuit formation. Greater functionality is obtained from an integrated circuit by forming a greater number of transistors in the same amount of space on an integrated circuit. Thus, a method is needed that forms a transistor which occupies less surface area of the silicon substrate of the semiconductor wafer.
It is also desired that transistors operate at lower voltage levels. One barrier to the formation of MOS transistors that operate at lower voltage levels is the channel length of MOS transistors. The channel length is generally determined by the width of a gate region of the MOS transistor being formed. The width of the gate region is, in turn, limited in conventional manufacturing processes by photolithography resolution limits as discussed above. The dimensions of the gate region also determines, to an extent, the amount of surface area that the transistor occupies. Accordingly, an improved process is needed which can manufacture transistors on integrated circuits with reduced gate length and with lower operational voltage levels.
The formation of transistors is also a complicated process, requiring numerous steps. The high number of steps required increases integrated circuit manufacturing process costs, reduces throughput, and presents more opportunities for error to occur. Therefore, a method for streamlining the transistor formation process is also needed.
Another shaped structure for which an improved method of formation is needed is a shallow trench that is often etched into a silicon substrate and which is used for forming semiconductor devices such as a trench isolation region and a trench capacitor. A method is needed of forming a trench capacitor that has an adequate volume and yet which does not occupy a large amount of surface area of the silicon substrate in order to provide high capacitance of the trench capacitor. A method of forming a trench with adequate volume would also improve a trench isolation region and help to prevent cross-talk current leakage between source/drain regions of MOS transistors that are typically formed on either side of the trench isolation region.
A further shaped structure that is frequently used in the construction of integrated circuits is the interconnect line. The term interconnect line, as used herein, refers to shaped structures that electrically connect semiconductor devices or features of semiconductor devices located on the same level, or that make electrical interconnections between interconnect structures formed on a single level of the semiconductor wafer, yet which are physically separated from each other. When formed on the top surface of the semiconductor wafer, this structure is referred to simply as a surface interconnect line. When formed beneath the surface of the semiconductor wafer, the interconnect line is referred to as a local interconnect.
One consideration in miniaturizing the integrated circuit is obtaining a more dense packing of the interconnect lines within the integrated circuit. One manner of more densely packing interconnect lines is to form the interconnect lines with a narrower width. Interconnect line widths are currently restricted by the resolution limits of conventional photolithography processes. One manner in which the prior art has attempted to overcome these limitations is with the disposable spacer flow process discussed above. As discussed therein, the thickness of the conducting lines formed with the disposable spacer flow cannot be varied. Consequently, when it becomes necessary to connect the conducting spacers to wider interconnect lines or to devices with larger feature sizes, no extra material is provided for doing so. Thus, a more flexible process for providing narrow interconnect lines is needed.
Other shaped structures are also frequently used in forming integrated circuits and would also benefit from an improved etching process whereby shaped structures could be formed with a more flexible, simple, and efficient process. One application for such shaped structures is in forming micro-machine parts as are commonly used in miniature sensors and actuators. A method is needed for forming such structures with a minimum of material deposition, masking, and etching steps.
A further shaped structure used in integrated circuit formation is a free-standing wall that is used to form capacitor storage nodes and other conducting devices. A method that provides flexibility as to the thickness of the resulting free-standing wall, and as to the shape with which the free-standing wall can be formed is needed. Such a method that can form the free-standing wall efficiently and with sub-photolithographic resolution is also needed.
To overcome the foregoing problems existing in the art, and in accordance with the invention as embodied and broadly described herein in the preferred embodiments, various methods are provided. In the invention, selected portions of a volume of a material, preferably composed of a silicon-containing material and/or a germanium-containing material, are selectively removed. The removal of the selected portions will preferably be by etching with an etchant, preferably a basic etchant, to form a shaped structure. A basic etchant is defined herein as an etchant having a pH greater than 7. In general, the distinction between removed and unremoved portions of the volume of material is the respective degree of internal stress. It is believed that the etchant will remove the high stress portion of the volume of material at a higher material removal rate than the etchant will remove the lower stress portion of the volume of material. As such, the high stress portion will be removed and than low stress portion will not be removed.
The invention is directed towards a volume of a material that is formed upon on a semiconductor substrate. The volume of the material is to have uniform stress throughout. The stress in a first portion of the volume of the material is reduced without reducing the stress in a second portion of the volume of the material. Preferably, the stress in the first portion is reduced by bombarding the first portion with atomic particles, such as by ion implantation. The second portion is then selectively removed. Preferably, the second portion is removed in an etch process. The etch process is performed upon the volume of the material, preferably with an basic etchant. Due to the respective degree of stress in each of the first and second portions, the etch will have a lower material removal rate for first portion than for the second portion. In general, regardless of the respective degree of any dopant concentration in the removed and unremoved portions prior to such stress reduction such as by bombardment or implantation, the distinction between removed and unremoved portions of the volume of material is the respective degree of stress.
In the following summary description of various inventive methods, the selective removal of a volume of a silicon-containing material is described. It is intended, however, that the invention is also applicable to a volume of a germanium-containing material
In a first method, a selected portion of a volume of silicon-containing material located on a semiconductor substrate is removed in such a manner as to leave a shaped opening in the layer of silicon-containing material. Initially, a layer of silicon-containing material, which in one embodiment comprises a polysilicon layer, is provided on a semiconductor substrate. A masking substrate is formed on the layer of silicon containing material that masks at least one region of the layer of silicon-containing material and leaves a second region of the layer of silicon-containing material unmasked.
Ions of a selected type are then implanted into the unmasked portion of the layer of silicon-containing material. The ions are of a type that is selected in accordance with an etching process which is selective to implanted silicon-containing material in a manner which will hereafter be discussed. In order to reduce the dimensions of the shaped opening from the dimensions of the masking substrate, the ions can be implanted with an angle of implantation other than orthogonal to the semiconductor substrate, causing the ions to be implanted under the edges of the masking substrate. Implanting the ions with an angle of implantation other than orthogonal to the semiconductor substrate will result in a reduction in the dimensions of the shaped opening from the dimensions of the masking substrate, while an angle of implantation orthogonal to the surface of the semiconductor substrate results in no substantial dimension change.
Other ion implantation parameters, such as ion type, implantation dose, and implantation energy can also be appropriately selected to further tailor the dimensions of the implanted region and thereby the resulting shaped opening. The impermeability to ions of the selected masking material also has an effect in sculpting the resulting shaped structure. Diffusing the ions after ion implantation with a heat treatment deepens the penetration of the ions into the polysilicon layer and further serves to tailor the profile of the resultant shaped feature, though it is generally preferred not to heat treat in order to maintain a sharper profile of the implanted ions in the layer of silicon-containing material.
Additionally, in order to vary the dimensions in a uniform manner, the ion implantation operation can be conducted in multiple implantation stages with one ion implantation parameter being varied for each implantation stage. By varying the angle of implantation for each of the multiple implantation stages, for instance, deep shaped openings can be formed with substantially anisotropic sidewalls.
The masking substrate in a subsequent procedure is stripped from the layer of silicon-containing material, and the layer of silicon-containing material is then etched with an etching process. The etching process etches portions of a volume of silicon-containing material that are not implanted with ions to a threshold concentration at a faster rate than the etching process etches portions of the volume of silicon-containing material that are implanted with ions up to the threshold concentration. Such an etching process is referred to in this document as an etching process which is selective to implanted silicon-containing material. The exact concentration which constitutes the threshold concentration varies in accordance with the particular etching process and the etching process parameters. Nevertheless, for any such etching process, silicon-containing material implanted with ions beyond the threshold concentration is not substantially removed by the etching process which is selective to implanted silicon-containing material, and silicon-material implanted to less than the threshold concentration is substantially removed.
In etching processes that are selective to low stress portions of a volume of a material and that etch high stress portions of the volume of the material, preferred etchants include an etchant having a pH greater than 7 and more preferably not less than 9, an organic base, an inorganic base, an etchant that contains ammonia, a basic etchant that does not contain Group I or Group II metals, tetraethylammonium hydroxide, tetrabutylphosphonium hydroxide, tetraphenylarsonium hydroxide, KOH, NaOH, and tetramethyl ammonium hydroxide (TMAH). Preferably, the etched material is a silicon-containing material or a germanium containing material. Although the invention discussed below expands upon the use of TMAH as an etchant, the foregoing etchants are also contemplated in processes of forming the various structures described below.
Where the etching process is selective to implanted silicon-containing material and the etchant is TMAH, a wet etch is preferred. The TMAH wet etch is typically administered as an etchant solution into which the semiconductor wafer is immersed. Preferably, the etchant solution comprises about 1 to about 10 weight percent of TMAH in deionized water. More preferably, the etchant solution comprises about 2.5 weight percent of TMAH in deionized water.
The TMAH wet etch has been found to etch silicon-containing material implanted to less than the threshold concentration of ions at least two times faster than it etches silicon-containing material that is implanted to the threshold concentration of ions. Differences in etch rates of 20 to one and 40 to one are easily achievable, and a difference in etch rates of up to 60 to one can be obtained according to TMAH concentrations and the selection of other ion implantation and etching process parameters.
When conducting the TMAH wet etch for polysilicon, the threshold concentration of implanted ions at least to polysilicon is implanted is preferably in a range from about 1xc3x971015 ions per cm3 of silicon-containing material to about 1xc3x971022 per cm3 of silicon-containing material. More preferably, the threshold concentration is in a range from about 5xc3x971018 ions per cm3 of silicon-containing material to about 5xc3x971019 ions per cm3 of silicon-containing material. Most preferably, the threshold concentration is about 1xc3x971019 ions per cm3 of silicon-containing material.
Common dopants such as boron and phosphorous are suitable for use as the implanted ions, and in addition, other common dopant ions and even ions that are not commonly considered to be dopant ions are satisfactory. For instance, ions can also be successfully used in conjunction with the TMAH wet etch that do not electrically activate or otherwise alter the electrical properties of the silicon-containing material. Examples of such ions are silicon ions and argon ions.
As a result of the etching process which is selective to implanted silicon-containing material, a selected portion of the polysilicon layer that is not implanted up to the threshold concentration of ions is etched away to form a shaped opening. Etching process parameters, such as the duration of the etch, can also be varied to further tailor the shaped opening. In one example of the use of a shaped opening, an ovonic cell of a programmable resistor is formed by filling the shaped opening with chalcogenide material.
In a related embodiment, the polysilicon layer with the shaped opening therein is used as a hard mask to pattern an underlying layer. Thus, for example, a layer of material other than a silicon-containing material such as a layer of silicon nitride is initially formed under the layer of silicon-containing material, and the first method is carried out to create a shaped opening in the layer of silicon-containing material. An etching process is then conducted to etch the layer of silicon nitride through the shaped opening to form a shaped opening in the layer of silicon nitride.
Thus, a method is provided for forming shaped openings which are simple and efficient. The method can be used to form shaped openings with smaller dimensions than can be formed with conventional photolithography processes. Greater flexibility is provided as to the possible profiles of the resulting shaped openings, thereby increasing the types of semiconductor devices that can be formed thereby, and consequently, the potential functionality of the integrated circuit formed with the first method.
In a second method of the present invention, a shaped structure is formed from a layer of silicon-containing material on a semiconductor wafer with an etching process that, converse to the etching process of the first method, etches silicon-containing material that is implanted with ions up to a threshold concentration at a substantially faster rate than it etches silicon-containing material that is not implanted with ions up to the threshold concentration. The second method initially comprises providing a layer of silicon-containing material, such as a polysilicon layer, on a semiconductor substrate. Thereafter, a masking substrate is formed over the layer of silicon-containing material. The masking substrate is formed so as to cover at least a portion of the layer of silicon-containing material and to leave a portion of the layer of silicon-containing material unmasked.
Subsequently, ions are implanted into the unmasked portion of the layer of silicon-containing material. The ions are of a selected type chosen in accordance with an etching process which is selective to unimplanted silicon-containing material. In one embodiment, the ions comprise dopant ions such as phosphorous or boron ions. As with the first method, the ion implantation operation can be conducted with ion implantation parameters selected to tailor the profile of the portion of the layer of material that is implanted to the threshold concentration, and thereby of the resulting shaped structure. The ion implantation operation can also be conducted in multiple implantation stages with the ion implantation parameters varied for each of the multiple implantation stages as previously discussed for the first method.
After the ion implantation operation is conducted, an initial etching process is thereafter conducted that etches the layer of silicon-containing material substantially anisotropically to partially reduce the height of the unmasked portion of the layer of silicon-containing material.
Once the initial etching process is conducted, the layer of silicon-containing material is etched with an etching process which etches portions of the layer of silicon-containing material that are implanted with ions up to a threshold concentration at a substantially faster rate than it etches portions of the layer of silicon-containing material that are not implanted with ions up to the threshold concentration. Such etching processes are referred to herein as an etching process which is selective to unimplanted silicon-containing material. The concentration of ions which constitutes the threshold concentration is determined by the particular etching process which is selective to unimplanted silicon-containing material that is used and by the selection of the ion implantation and etching parameters in a manner that will be readily understood from this disclosure by those skilled in the art.
In one embodiment given by way of example, the etching process which is selective to unimplanted silicon-containing material uses an acidic etchant such as commercially available hydrofluoric acid, or it may use a nitric acid etchant solution. Also, a KOH etching chemistry can be used together with a counter-doping of the polysilicon layer.
The result of the etching process which is selective to unimplanted material is a raised shaped structure formed in the location of the portion of the layer of silicon-containing material that was masked and thus implanted to less than the threshold concentration of ions. In the embodiment wherein ions are implanted at an angle other than orthogonal to the surface of the semiconductor substrate, the shaped structure has dimensions that are reduced from the dimensions of the masked portion of the layer of silicon-containing material.
The raised shaped structure can also be used as a sacrificial hard mask for etching an underlying layer. When using the raised shaped structure as a sacrificial hard mask, an underlying layer is formed prior to depositing the layer of material. The raised shaped structure is then formed in the manner discussed above, and serves as a hard mask when etching the underlying layer. The underlying layer is typically etched anisotropically, with an etching process such as dry etching. The raised shaped structure is removed after etching the underlying layer, and a portion of the underlying layer remains in substantially the same location and with substantially the same dimensions as the raised shaped structure. Once again, these dimensions can be smaller than those of which conventional photolithography is capable.
A third method of the present invention is used to form an interconnect structure. Under the third method, a charge conducting region such as an active region is first provided on a semiconductor substrate. A layer of silicon-containing material, which in one embodiment is a polysilicon layer, is then formed over the charge conducting region. The layer of silicon-containing material is then masked with a masking substrate that is patterned so as to leave masked a portion of the layer of silicon-containing material that is located over the active region.
After the masking substrate is applied, ions are implanted into the unmasked portion of the layer of silicon-containing material. The ions are selected, as discussed above for the first method, in conjunction with an etching process which is selective to unimplanted silicon-containing material. The ion implantation process parameters can be varied to shape the resulting interconnect structure. Also, the ion implantation operation can be conducted in multiple implantation stages as discussed above.
After the ion implantation operation is concluded, the masking substrate is removed, and the layer of silicon-containing material is etched with the etching process which is selective to unimplanted silicon-containing material. As a result, the portion of the layer of silicon-containing material that was underlying the masking substrate is removed, and the portion of the layer of silicon-containing material located above the active region, which was masked and thus was unimplanted with ions, remains and forms the interconnect structure electrically connected to the active region.
The interconnect structure is, as a result of the method of the present invention, constructed in a more simple and efficient manner than interconnect structures constructed with the conventional methods discussed above. Accordingly, integrated circuit manufacturing throughput is increased and integrated circuit manufacturing cost is reduced. The need for a dry etching process and the problems associated therewith, as discussed above, are also eliminated.
A fourth method of the present invention is used to form a stacked capacitor storage node. Under the fourth method, a charge conducting region is initially provided on a semiconductor substrate, above which the stacked capacitor storage node is to be formed. In one embodiment, the charge conducting region comprises an active region formed in a silicon substrate of a semiconductor wafer. Once the active region is provided, a layer of silicon-containing material is then formed over the active region. In the embodiment to be discussed, the layer of silicon-containing material comprises a polysilicon layer.
The polysilicon layer is subsequently masked with a masking substrate that is patterned so as to leave a portion of the polysilicon layer located above the active region unmasked. The masking substrate is formed with an island having two edges, each located above and to one side of the active region.
After the masking substrate is applied and patterned, spacers of silicon-containing material are formed on the polysilicon layer, one adjacent each of the two edges of the masking substrate. The spacers are formed with a conventional spacer formation process, and their shape and height are selected in accordance with the needs of the stacked capacitor storage node being formed.
Thereafter, ions are implanted into the unmasked portion of the polysilicon layer, substantially in the manner discussed above for the first method. Also, the ion implantation operation can be conducted in multiple stages as discussed above.
After the ion implantation operation is concluded, the masking substrate is removed and the polysilicon layer is etched with the etching process which is selective to implanted silicon-containing material in the manner discussed above for the first method. The etching process which is selective to implanted silicon-containing material removes the portions of the polysilicon layer that were underlying the masking substrate and allows the portion of the polysilicon layer located above the active region that was unmasked to remain. The spacers also remain and extend upward therefrom to form the stacked capacitor storage node.
In an alternate embodiment of the fourth method, an interconnect structure is formed concurrently with stacked capacitor storage node formation. The procedure is substantially the same as that of the first embodiment wherein only a stacked capacitor storage node is formed, with the exception that in the location where an interconnect structure is to be formed, spacers are not formed above the portion of the polysilicon layer where the interconnect structure is to be located. The ion implantation process parameters can be varied to shape the resulting interconnect structure.
The fourth method forms a stacked capacitor storage node with an integral storage node and capacitor base thereby providing a greater storage area for greater charge retention. The stacked capacitor storage node can be formed concurrently with the capacitor base, thereby eliminating a separate interconnect structure formation step. Consequently, the number of masking and etching steps is decreased, which in turn increases the throughput, reduces the cost, and eliminates opportunities for error in the integrated circuit fabrication process. The fourth method also introduces greater flexibility to the stacked capacitor storage node formation process, as polysilicon plugs can be formed over active regions concurrently with the formation of the stacked capacitor storage node.
A fifth method is provided herein and is used to form an interconnect structure in a CMOS process flow. Under the fifth method, a conventional CMOS integrated circuit formation process is followed up to the point of transistor gate regions formation. In so doing, a silicon substrate is formed with a PMOS portion and an NMOS portion. At least one gate region is formed on each of the PMOS portion and the NMOS portion. Insulating spacers may also be formed around the gate region of the NMOS portion. The PMOS portion is then masked with a first masking substrate.
Dopant ions of a suitable type are thereafter implanted into the NMOS portion to create at least one active region therein. Thereafter, the first masking substrate is removed from the PMOS portion, and a layer of silicon-containing material is deposited over the PMOS and NMOS portions. In the embodiment to be discussed, the layer of silicon-containing material is a polysilicon layer.
Once deposited, the polysilicon layer is masked with a second masking substrate. The second masking substrate is patterned so as to leave unmasked a portion of the polysilicon layer located above a selected active region of the NMOS portion.
Subsequently, ions are implanted into the unmasked portion of the polysilicon layer. In so doing, the second masking substrate prohibits ions from substantially impinging into and implanting the portions of the polysilicon layer underlying the masking substrate. The ion implantation operation is conducted substantially as described above for the first method. The second masking substrate is then removed, and the polysilicon layer is etched with the etching process which is selective to implanted silicon-containing material, thereby removing the portions of the polysilicon layer that were underlying the masking substrate. The unmasked portion of the polysilicon layer above the selected active region of the NMOS portion remains and forms a polysilicon interconnect structure.
The ion implantation and etching process parameters can be appropriately selected in the manner discussed in the description of the first method above. Once again, the ion implantation operation can be conducted at an angle other than orthogonal to the silicon substrate, and can be conducted in multiple stages. The type of masking substrate may also be varied and the implanted ions can optionally be diffused by heat treatment to further tailor the shape of the resulting interconnect structure.
Once the interconnect structure is formed, the NMOS portion is covered with a masking substrate, and ions are implanted into the PMOS portion to form at least one active region therein.
Thus, under the fifth method, an interconnect structure is formed in a CMOS process flow that eliminates several steps required by conventional prior art methods. Also, the source/drain regions of the NMOS and PMOS regions are doped without cross-contamination from the ion implantation or etching processes. The number of masking and etching operations is reduced from the conventional CMOS process flow, thereby increasing throughput of the integrated circuit manufacturing process and ultimately reducing the cost of the integrated circuits formed thereby. The fifth method is also simple and efficient and leads effectively into contact etch and capacitor formation.
A sixth method of the present invention is used to form a free-standing wall. The free-standing wall is suitable for use in forming a stacked capacitor storage node. Under the sixth method, a layer of silicon-containing material, which is a polysilicon layer in the embodiment to be described, is initially deposited upon a semiconductor substrate. The polysilicon layer is preferably formed of intrinsic polysilicon.
After forming the polysilicon layer, a masking substrate is applied over the polysilicon layer and is patterned to form a mask island. A dry etching process is then used to anisotropically remove the exposed portion of the polysilicon layer. The dry etching process forms a polysilicon block out of the polysilicon layer that has surface dimensions corresponding to the surface dimensions of the island of the masking substrate.
After the dry etching process is concluded, one or more of the laterally extending surfaces of the polysilicon block are implanted with ions with the masking substrate remaining in place. Following the ion implantation operation, the masking substrate is removed and an etching process is conducted which is selective to implanted silicon-containing material is conducted. Depending on the shape of the polysilicon block and the extent of the laterally extending surfaces of the polysilicon block that is implanted, a variety of differently shaped free-standing walls can be formed. By forming the polysilicon block with the appropriate shape, for instance, thin and laterally extending polysilicon columns can be formed, pairs of which are suitable for forming container capacitors. Thin posts can also be created which are characterized as columns of relatively small thickness.
When the entire periphery of the polysilicon block is implanted, continuously extending free-standing walls are formed. If the polysilicon block is circular, an annular free-standing wall is formed. The thickness of the resulting free-standing wall is determined by the angle of implantation and the implantation energy of the implanted ions. Consequently, the free-standing wall can have sub-photolithography resolution thickness dimensions.
The free-standing wall of the sixth method can be formed with a high aspect ratio of which conventional photolithography and etching methods are incapable. The capability of forming the free-standing wall with a variety of shapes adds a flexibility to the integrated circuit formation process. Additionally, the free-standing wall is formed in an efficient manner with a minimum of processing operations, thereby maintaining a high throughput and low cost of the integrated circuit manufacturing process.
A seventh method of the present invention is similar to the sixth method, and is also used to form a free-standing wall that is suitable for forming a stacked capacitor storage node. The seventh method involves initially depositing a polysilicon layer as in the sixth method, and thereafter applying and patterning a masking substrate over the polysilicon layer. The masking substrate is as in the seventh method, but it is also patterned with an opening to form a corresponding patterned opening in the polysilicon layer. Directional ion implantation is then conducted to implant ions into the laterally extending surface of the opening in the polysilicon layer with the masking substrate in place. The ion implantation operation is conducted substantially in the manner described above for the first method, and is conducted with an angle of implantation other than orthogonal to the surface of the semiconductor substrate in order to implant the laterally extending surface of the opening in the polysilicon layer. The masking substrate is thereafter removed, and the etching process is conducted which is selective to implanted silicon-containing material which is substantially in the manner described above in the first method, and results in a free-standing wall.
The free-standing wall can be formed with a variety of configurations, depending on the shape of the masking substrate opening and the extent to which the laterally extending surface of the shaped opening in the polysilicon layer is implanted. For instance, by forming a circular masking substrate opening and implanting the entirety of the laterally extending surface of the opening in the polysilicon layer, an annular free-standing wall can be formed such as is suitable for forming a stacked capacitor storage node or a surround-gate transistor gate region. Thus, the free-standing wall of the seventh method has similar advantages to the sixth method, and provides an added flexibility to the integrated circuit manufacturing process.
An eighth method of the present invention is used to form a surround-gate MOS transistor. Initially under the eighth method, a free-standing wall is created, preferably in a manner described above for either the sixth or the seventh method. The free-standing wall is preferably continuous, defining a chamber therein and could be of any suitable shape, including rectangular or hexagonal. The preferred shape is annular. The free-standing wall is formed on the semiconductor substrate over a gate oxide layer, after which a continuous insulating spacer is formed on either side of the free-standing wall. Dopants are then implanted into the silicon substrate at the interior of the free-standing wall and around the exterior of the free-standing wall. The dopants are selected as N-type or P-type dopants, depending on whether the transistor being formed is an N-channel or P-channel transistor, respectively. The implanted interior and exterior of the free-standing wall region form the source/drain regions of the surround-gate transistor.
Formed thereby is a surround-gate transistor, with a gate region formed from the free-standing wall, a source/drain region formed at the interior of the gate region, and another source/drain region formed at the exterior of the gate region, surrounding the gate region. A MOS transistor channel extends under the gate region, and has a short channel length determined by the thickness of the free-standing wall. As the thickness of the free-standing wall is not dependent upon conventional photolithography resolution levels, the MOS transistor channel can correspondingly be quite short. Preferably, the channel has a length of less than about 0.25 microns.
A DRAM memory cell can also be formed under the eighth method. In so doing, the surround-gate transistor is formed as described, and a word line is connected with the gate of the surround-gate transistor. A lower insulating layer is then formed over the surround-gate transistor. Interconnect structure openings are opened through the lower insulating layer down to the source/drain regions of the surround-gate transistor. The interconnect structure openings are filled with conductive material to form contacts. One contact is constructed extending down to the source/drain region at the interior of the gate region, and a second is constructed extending down to the source/drain region at the exterior of the gate region.
In a further procedure of forming the DRAM memory cell, a storage node is formed over the lower insulating layer, connecting with the contact extending down to the source/drain region at the interior of the gate region. A dielectric layer is formed over the storage node, and an upper capacitor plate is formed over the dielectric layer. An upper insulating layer is then formed over the capacitor, and a digit line is formed at the top thereof connected with the contact that extends down to the source/drain region at the exterior of the gate region.
The MOS surround-gate transistor occupies a minimum of space on the semiconductor substrate, and is formed in a simpler and more efficient manner than surround-gate transistors of the prior art. The MOS surround-gate transistor can be formed with a short MOS transistor channel, which can be of a length of less than about 0.2 microns. The MOS surround-gate transistor is easily incorporated into a DRAM memory cell, which, similar to the MOS surround-gate transistor, occupies a minimum of surface area on the semiconductor substrate. The DRAM memory cell also exhibits a low amount of leakage due to the placement of the capacitor over the center of the MOS surround-gate transistor.
A ninth method of the present invention is used to form a cone shaped free-standing wall that is suitable for use as a stacked capacitor storage node. Under the ninth method, a layer of silicon-containing material, which is a polysilicon layer in the embodiment to be discussed, is initially deposited upon a semiconductor substrate. In the discussed embodiment, the semiconductor substrate is a silicon substrate which has gate regions formed thereon to the sides of active regions also formed thereon. The polysilicon layer is preferably formed of intrinsically doped polysilicon. After deposition of the polysilicon layer, an insulating layer is formed over the polysilicon layer.
Once the insulating layer is formed, a masking substrate is deposited and patterned over the insulating layer. The masking substrate is patterned with an opening at the location wherein the conical stacked capacitor storage node is to be formed. A dry etching process is then used to etch the exposed region of the polysilicon layer in a sloping fashion. A conical opening is thereby formed in the polysilicon layer that tapers down to an active region in the silicon substrate. After the dry etching process is concluded, the masking substrate is removed and a second polysilicon layer is deposited over the first polysilicon layer and over the insulating layer. The second polysilicon layer is then implanted with ions in the manner discussed for the first method above to form an implanted region therein.
The uppermost portion of the second polysilicon layer and the insulating layer are thereafter removed by planarization. Following planarization, the etching process discussed above which is selective to implanted silicon-containing material is conducted. In substantially the same manner as described for the first method above, a free-standing wall is thus formed having a high aspect ratio, a conical shape, and a small area of contact with the underlying active region, thereby occupying a minimum of space on the silicon substrate.
The ninth method is advantageous in that it eliminates a masking and material deposition operation from the prior art stacked capacitor storage node formation processes, thereby increasing throughput of the integrated circuit manufacturing process. The integrated circuit manufacturing process is thereby simplified, increasing yield and decreasing cost. The ninth method also has a relatively large alignment process window, further increasing yield and further facilitating greater miniaturization of the integrated circuit being fabricated.
A tenth method of the present invention uses the etching process which is selective to unimplanted silicon-containing material of the second method to form an interconnect structure. In the embodiment to be discussed, the layer of silicon-conducting material comprises a polysilicon layer. The polysilicon layer is preferably formed of intrinsic polysilicon. The tenth method initially involves forming active regions and gate structures on a semiconductor substrate. A lightly doped or undoped polysilicon layer is then formed over the gate structures.
Once the polysilicon layer is formed, a masking substrate is applied over the polysilicon layer and is patterned to cover a portion of the polysilicon layer located above a conducting region that is to be electrically connected by the polysilicon plug. In the discussed embodiment, the conducting region is an active region. A portion of the polysilicon layer that is to be removed is left exposed. After patterning the masking substrate, an anisotropic etching process is conducted through the openings in the masking substrate. The anisotropic etching process partially reduces the height of the portion of the polysilicon layer that is not covered by the masking substrate. Exposed portions of the polysilicon layer are consequently reduced to less than their original height.
An ion implantation operation is subsequently conducted substantially in the manner described above for the second method. The preferred type of ions to be implanted by the ion implantation process is arsenic ions. An etching process is conducted after implantation which is selective to unimplanted silicon-containing material as described for the second method above. Once again, the parameters of the selective etching process and the ion implantation operation can be appropriately selected to tailor the profile of the portion of the polysilicon layer that is implanted. An interconnect structure is thereby formed, such as a polysilicon plug that is formed in a more efficient and streamlined manner than the above-discussed methods of the prior art.
An eleventh method of the present invention uses the etching process which is selective to implanted silicon-containing material of the first method as well as a height reduction operation to form an interconnect structure. Under the eleventh method, a plurality of raised insulating surfaces are initially provided on a semiconductor substrate. In the embodiment to be discussed, the raised insulating surfaces comprise a plurality of gate regions. Silicon nitride caps are preferably formed on the tops of the plurality of gate regions. At least one charge conducting region, preferably an active region, is also provided between the gate regions at the bottom thereof. A polysilicon layer is then formed over the active region and the gate regions which fills in an intervening open area located over the active region and between the gate regions.
In a subsequent procedure of the eleventh method, the height of the polysilicon layer is reduced down to the level of the tops of the gate regions, preferably with a planarization process. The planarization process more preferably comprises chemical mechanical planarization (CMP) which stops on the silicon nitride caps formed over the gate regions.
A masking substrate is, in subsequent procedure, formed over the polysilicon layer and the gate regions and is patterned with an opening over the portion of the polysilicon layer that overlies the active region above which the interconnect structure is to be formed. The opening in the masking substrate also slightly overlaps the tops of the gate regions. The opening is a thereby self-aligned in that a slight misalignment of the masking substrate will not result in a defect condition.
Ions of a type selected in accordance with the etching process which is selective to implanted silicon-containing material, as discussed for the first method, are then implanted into a selected segment of the polysilicon layer that overlies the active region. The nitride spacers prevent the ions from being implanted into the gate regions, and consequently also assist in self-alignment.
The masking substrate is then removed and the etching process which is selective to implanted silicon-containing material is conducted in a manner substantially as described above for the first method. The etching process which is selective to implanted silicon-containing material removes the polysilicon layer except for the selected segment overlying the active region that was implanted with ions. The remaining selected segment that is not etched away forms an interconnect structure. In the discussed embodiment, the interconnect structure is a polysilicon plug that extends from the active region up to the level of the tops of the gate regions.
The eleventh method simplifies the interconnect structure formation process by eliminating the BPSG deposition, reflow, and dry etching steps of the prior art polysilicon plug formation process discussed above. The streamlined process increases integrated circuit fabrication process throughput and reduces costs. The problems associated with the dry etching process of the prior art and the formation of the high aspect ratio interconnect structure openings are also avoided.
A twelfth method of the present invention uses the etching process which is selective to implanted silicon-containing material of the present invention and a planarization process which stops on silicon nitride to form a sacrificial interconnect structure. In addition, the twelfth method further involves the subsequent removal of the self-aligned interconnect structure to form an extended depth interconnect structure opening.
Initially in the twelfth method, a sacrificial interconnect structure is formed, preferably in the manner described above for the eleventh method, and is used as a removable xe2x80x9cdummyxe2x80x9d in forming an extended depth interconnect structure opening. In the twelfth method, a thin insulating layer is formed over a semiconductor substrate surface. A charge conducting region which is to be provided with electrical contact through the extended depth interconnect structure opening is located beneath the thin insulating layer, central to a plurality of raised insulating surfaces. An intervening open area is thus formed above the charge conducting region in between the plurality of raised insulating surfaces.
Thereafter, a sacrificial interconnect structure is formed in the intervening open area extending from the charge conducting regions to the tops of the raised insulating surfaces. The sacrificial interconnect structure is preferably formed in the manner described for the eleventh method. Once the sacrificial interconnect structure is formed, a blanket layer of insulating material is formed over the interconnect structure.
In one embodiment to be discussed, the semiconductor substrate is a silicon substrate, the charge conducting region is a source/drain region, the sacrificial interconnect structure is a polysilicon plug, and the raised insulating surfaces are gate regions. The gate regions are preferably provided at the tops thereof with silicon nitride caps. Once the polysilicon plug is formed over the source/drain region, a blanket layer of insulating material is formed over the polysilicon plug extending over and a distance above the polysilicon plug.
An interconnect structure opening is then formed through the blanket layer of insulating material extending down to the top of the polysilicon plug, thereby exposing the top of the polysilicon plug. In one manner of so doing, a masking substrate is applied and patterned, and an etching process is conducted which etches the material of the blanket layer of insulating material selective to polysilicon. In order to form the polysilicon plug in a self-aligned manner, the etching process is also preferably selective to the silicon nitride caps at the tops of the gate regions. The interconnect structure opening can be formed wider than the polysilicon plug, as the silicon nitride caps at the tops of the gate regions will stop the etching process from penetrating into the gate regions. Consequently, a leeway of approximately half the width of the gate structures is provided for the possibility of misalignment of the interconnect structure opening.
The polysilicon plug is then removed to expose the underlying source/drain region. The polysilicon plug is preferably removed using an etching process that selectively etches polysilicon and does not etch the blanket layer of insulating material or the material of the gate region caps. The etching process is also preferably selective to the material of the thin insulating layer in order to allow the thin insulating layer to function as an etch barrier and to prevent over-etching into the underlying source/drain region. One such etching process uses an etchant comprising a TMAH wet etch. The TMAH wet etch removes the polysilicon plug selective to the blanket layer of insulating material and the silicon nitride caps at the tops of the gate regions.
Once the polysilicon plug is removed, an extended depth self-aligned interconnect structure opening is formed in the location of the polysilicon plug, and extends from the source/drain region up to the top of the blanket layer of insulating material. The extended depth interconnect structure opening is in one embodiment filled with aluminum to form an aluminum contact. The extended depth interconnect structure is particularly useful in the formation of a stacked capacitor, where it is desirable that the base of the stacked capacitor be integral to the storage node of the stacked capacitor. Forming the base of the stacked capacitor integral to the storage node thereof provides a higher cell capacitance, as compared to stacked capacitors formed with non-integral polysilicon plugs of the prior art.
A thirteenth method of the present invention uses the etching process which is selective to implanted silicon-containing material of the first method to form a stacked capacitor storage node that has a large surface area. The thirteenth method initially involves forming an interconnect structure extending down through a planarized lower insulating layer to a charge conducting region on a semiconductor substrate. The interconnect structure is preferably formed in the manner described in the eleventh method, wherein a polysilicon plug is formed extending down to an active area between a pair of gate regions on a silicon substrate of a semiconductor wafer.
Once the polysilicon plug is formed, an upper insulating layer is deposited over the polysilicon plug and the gate regions. The upper insulating layer is then planarized, and an opening is formed in the upper insulating layer extending down to the tops of silicon nitride spacers located on the tops of the gate regions. The opening overlaps the silicon nitride spacers, allowing the opening to be self-aligned to the polysilicon plug that is located between the gate regions. The opening also exposes the top of the polysilicon plug. The opening is preferably circular, with a horizontal bottom and vertically extending sides.
After the opening is formed, a lower silicon-containing layer is formed over the surface of the opening. The lower silicon-containing layer is intrinsically doped with impurities that cause the etching process which to etch the lower silicon-containing layer slowly, where the etching is selective to implanted silicon-containing material discussed above for the first method. An intermediate silicon-containing layer, which is only lightly doped or which is not doped, is then formed over the lower polysilicon layer. An upper silicon-containing layer is then formed over the intermediate silicon-containing layer and is doped in a similar manner to the doping of the lower insulating layer. Each of the lower, intermediate, and upper polysilicon layers preferably comprise a horizontally extending bottom section and a vertically extending side section extending upward from the edges of the bottom section. Each of the lower, intermediate, and upper silicon-containing layers preferably comprise polysilicon.
Ions are subsequently implanted into the bottom section of the intermediate silicon-containing layer. In so doing, ions can also be implanted into the lower and upper silicon-containing layers with no detrimental effects. The ions of the ion implantation operation are preferably implanted with an angle of implantation orthogonal to the plane of the substrate, and with a selected implantation energy range. The selected implantation energy range is selected such that portions of the lower and upper side sections that extend above the surface of the opening will block the implanted ions from impacting the side sections of the intermediate silicon-containing layer. The side sections of the upper silicon-containing layer also block implanted ions from impacting the outer edges of the bottom section of the intermediate silicon-containing layer that underlie the side sections of the upper polysilicon layer. Accordingly, only a central portion of the bottom section of the intermediate silicon-containing layer is implanted with ions.
Portions of the lower, intermediate, and upper silicon-containing layers which are formed above the top of the upper insulating layer are then removed with a height reduction process such as planarization. Alternatively, there could be an over polish to further remove the intermediate layer which might have been impacted by the implant. An etching process which is selective to implanted silicon-containing material is then conducted to remove relatively unimplanted portions of the intermediate polysilicon layer. The central portion of the bottom section of the intermediate polysilicon layer which was implanted with ions is left remaining, while the outer edges of the bottom section and the sidewalls of the intermediate silicon-containing layer which were not implanted with ions are etched away. Thus, the entirety of the sidewalls and a portion of the bottom sections of the lower and upper polysilicon layers are exposed, increasing the surface area of the storage node. A shaped structure is formed thereby with a large surface area that makes the shaped structure highly suitable for use as a storage node of a stacked capacitor. In completing a stacked capacitor, a thin dielectric layer is formed over the storage node, and a cell plate is formed over the thin dielectric layer.
The storage node is formed in a streamlined and efficient manner, with only a single etching process that is conducted with a simple wet etch. The storage node has a large surface area, yet occupies a minimum of space on the semiconductor substrate.
A fourteenth method of the present invention uses the etching process which is selective to implanted silicon-containing material of the first method, and forms a stacked capacitor storage node with a free-standing wall having a thickness determined by the selection of a set of implantation parameters of an ion implantation operation. The stacked capacitor storage node is also formed with a roughened surface for greater surface area. The fourteenth method initially involves providing a semiconductor substrate and a charge conducting region to which the stacked capacitor storage node will be connected. In one embodiment, the semiconductor substrate comprises a silicon substrate of a semiconductor wafer and the charge conducting region comprises an active region located on the semiconductor substrate. It is preferred that a pair of gate regions be formed on the silicon substrate, one at either side of the active region. A layer of insulating material is then formed over the gate regions and the active region with a depth corresponding to a height to which the storage node is desired to extend above the gate regions.
Once formed, the insulating layer is thereafter planarized and an opening is formed in the insulating layer extending down to the charge conducting region. The opening preferably is self-aligned to the pair of gate regions in the manner of the thirteenth method.
A polysilicon layer is subsequently formed in the opening. The polysilicon layer is preferably a blanket layer and is deposited with a thickness that only partially fills the opening. The thickness of the polysilicon layer is selected in accordance with a desired thickness of the stacked capacitor storage node sidewalls to be formed and with an etching process which is selective to implanted silicon-containing material.,
An ion implantation process is then conducted in the manner described in the discussion of the first method. The ions are implanted into an outer portion of the polysilicon layer and are not implanted into an inner portion thereof. In order to do so, the ions are preferably implanted at an angle other than orthogonal to the plane of the semiconductor wafer. The ions are also implanted with an implantation energy selected in conjunction with the angle of implantation to implant the polysilicon layer to a desired depth. The desired depth corresponds to a thickness of a resulting free-standing wall of a stacked capacitor storage node that is to be formed from the polysilicon layer. The ion implantation can be conducted in stages with the ion implantation parameters varied between the stages to tailor the shape of the implanted portion as was discussed for the first method.
The remainder of the opening is thereafter filled with photoresist or other suitable material in preparation for conducting a height reduction process. The photoresist or other suitable material protects the polysilicon in the opening from being contaminated by the height reduction process. The height reduction process is then conducted to remove portions of the polysilicon layer that extend above the top of the insulating layer. The height reduction process is preferably a planarization process and more preferably is a CMP process.
The surface area of the stacked capacitor storage node is increased by roughening the polysilicon layer at this stage or at a later stage in the fourteenth method. To do so, a layer of hemispherical or cylindrical grain polysilicon is preferably deposited with a chemical vapor deposition (CVD) process on the polysilicon layer in the opening.
In a further procedure, the etching process which is selective to implanted silicon-containing material is conducted and removes the unimplanted inner portion of the polysilicon layer. The implanted outer portion of the polysilicon layer remains in place and forms a free-standing wall around the opening without physically contacting the opening except at the bottom of the opening, where it may contact the gate regions and is in electrical communication with the underlying charge conducting region. Preferably, the opening is circular, and consequently, the free-standing wall is annular.
If the interior of the free-standing wall was not roughened at a prior stage of the fourteenth method, it can be roughened at this point. As both an inner face and an outer face of the polysilicon layer are now exposed, hemispherical or cylindrical grain polysilicon is formed on both the inner face and on the outer face of the free-standing wall. Roughening the free-standing wall surface at the prior stage results in only the inner face being roughened. Accordingly, roughening at this later stage is preferred over roughening in the prior stage.
Once the stacked capacitor storage node is formed, conventional process flow is followed to complete a stacked capacitor. Briefly, completion of a stacked capacitor involves forming a dielectric layer over the storage node, and forming a layer of polysilicon or other charge conducting material over the dielectric layer.
The fourteenth method is advantageous in that the stacked capacitor formed thereby has a large surface area, yet consumes minimal space on the silicon substrate of the semiconductor wafer. The method is simple and can be conducted so as to provide for high throughput and low cost of the integrated circuit fabrication process.
A fifteenth method of the present invention uses the etching process which is selective to implanted silicon-containing material of the first method along with multiple ion implantations of differing ranges of depth or otherwise in different patterns to form shaped polysilicon structures. The manner of formation of several representative shaped structures formed by variations of the basic embodiment of the fifteenth method are discussed herein.
The basic embodiment of the fifteenth method initially involves providing a volume of silicon-containing material. In the embodiments discussed herein, the volume of silicon-containing material comprises a polysilicon layer. Once the polysilicon layer is provided, a first selected region of the polysilicon layer is implanted with ions to a first depth range. A second selected region of the polysilicon layer is then also implanted with ions to a second depth range. The second depth range is preferably implanted with a lower implantation energy range and extends less deeply into the polysilicon layer than the first depth range. After ion implantation, the polysilicon layer is etched with an etching process which is selective to implanted silicon-containing material to remove the unimplanted polysilicon. The etching process is conducted substantially as described above for the first method.
The first and second selected regions are left remaining and form a shaped structure. Other selected regions which are implanted with ions to a different depth range or which are patterned with a different profile can be added to the first and second regions to form shaped structures of varying conformations.
In one embodiment, a free-standing bridge is formed by implanting regions of the polysilicon layer to form two uprights and an intervening cross-bar extending therebetween. The free-standing bridge can be formed with multiple cross-bars of different heights. The multiple cross-bar free-standing bridge is suitable for use as a severable fuse and can be employed in forming a programmable read only memory device (PROM).
By forming a single upright and a cross-bar integrally attached to the upright, a lever is formed that is suitable for use in forming micromachines. Overlapping cross-bars which do not electrically contact each other can also be formed.
In a further embodiment, a polysilicon block with an integrally formed tunnel extending entirely through the bottom thereof is formed. The polysilicon block is shaped and formed with a dry etching process, and the tunnel is formed by implanting portions of the polysilicon block that are to remain and then selectively etching away the relatively unimplanted portions.
In a further embodiment, a tunnel is formed extending from the surface of the polysilicon layer down below the surface of the polysilicon layer. A portion of the polysilicon layer situated around the tunnel is oxidized, and a metal is deposited into the tunnel to result in a conducting interconnect line routed beneath the surface of a now oxidized polysilicon layer.
The fifteenth method provides the capability of forming a wide variety of conducting shaped structures in an efficient manner, thereby allowing for greater functionality of the resulting integrated circuit. The shaped structures of the fifteenth method are formed with a minimal number of material deposition, masking, and etching operations. The shaped structures are thus formed efficiently, consuming a minimum of integrated circuit manufacturing process time.
A sixteenth method of the present invention uses the etching process which is selective to implanted silicon-containing material of the first method to form a bottle shaped trench in a semiconductor substrate. The bottle shaped trench is useful for forming a trench capacitor and for forming a trench isolation region.
The sixteenth method initially involves forming a substantially anisotropic trench in a volume of silicon-containing material on a semiconductor substrate. In one embodiment to be described, the volume of silicon-containing material is a silicon substrate and the semiconductor substrate is a semiconductor wafer. Thus, in this embodiment, a silicon substrate is provided and a masking substrate is formed over the silicon substrate. In one embodiment, the masking substrate is a photoresist mask and is self-aligned to gate regions formed on either side of the trench. Ions are then implanted into the trench. The ions are preferably implanted at an angle of implantation other than orthogonal to the surface of the silicon substrate. The angle of implantation is selected such that the ions are primarily directed toward the bottom portion of the trench rather than toward the top of the trench. Consequently, the bottom of the trench is implanted to a greater extent than the top of the trench.
An etching process which is selective to silicon-containing material that is not implanted with ions of the selected type is then conducted substantially in the manner described above for the second method. Material from the implanted portions of the trench is thereby removed, expanding the bottom of the trench more than the top of the trench and giving the trench its bottle shape. The bottle-shaped trench can be used for various applications, including the formation of a trench capacitor and a trench isolation region.
When forming a trench capacitor, a storage node is deposited in the trench, followed by a dielectric layer and an upper capacitor plate to complete the trench capacitor. When forming a trench isolation region, the bottle-shaped trench is filled with insulating material. The insulating material can be formed by first growing a layer of silicon oxide on the trench sidewalls and then depositing an insulating material into the remainder of the trench.
The trench capacitor is thus formed with greater surface area than if a conventionally shaped trench were formed. The greater surface area is achieved without occupying additional surface area of the silicon substrate. It is also achieved with a simple and efficient process. The trench isolation region likewise is formed with a large volume, and consequently provides great isolation capability, without consuming a large amount of silicon substrate surface area. The large volume provides a high resistance to cross-talk current leakage without sacrificing semiconductor device density and miniaturization.
A seventeenth method of the present invention uses the etching process which is selective to implanted silicon-containing material of the first method. The seventeenth method forms a region of silicon-containing material on each of one or more exposed horizontal surfaces of a semiconductor substrate, while not forming a region of silicon-containing material on any exposed vertical surfaces.
The seventeenth method initially involves providing a semiconductor substrate on which is located a protruding structure having an exposed horizontal surface and an exposed vertical surface. The protruding structure can be, for instance, a gate region on a silicon substrate of a semiconductor wafer.
A layer of silicon-containing material is formed over the exposed horizontal surface and over the exposed vertical surface. The layer of silicon-containing material is, in one embodiment which is to be discussed, a polysilicon layer. The polysilicon layer is preferably intrinsic polysilicon.
Ions are, in a subsequent procedure, implanted into the portion of the polysilicon layer that is situated on the exposed horizontal surface. The ions are of a type selected in accordance with an etching process which is selective to implanted polysilicon as described for the first embodiment. The ions are preferably implanted with an angle of implantation that is orthogonal to the exposed horizontal surface.
The implantation of ions at an orthogonal angle causes portions of the polysilicon layer situated on the exposed horizontal surface to be implanted with ions and does not substantially implant ions into a portion of the polysilicon layer situated over the exposed vertical surface.
In a subsequent procedure, the etching process is conducted which is selective to implanted silicon-containing material which is described above in the discussion of the first method. Thus, the portion of the polysilicon layer that was situated over the exposed vertical surface and was thus not implanted with ions is etched away. The portion of the polysilicon layer that is located over the exposed horizontal surface and was thus implanted with ions is left remaining.
Several applications of the seventeenth method are provided. In one application, the vertically protruding feature is a gate region of a MOS transistor, and a polysilicon region is formed on the horizontal surfaces of the gate region for use as an implant mask for a halo implant to provide punch-through protection.
In a further application, polysilicon regions are formed on horizontal surfaces for use as interconnect lines. When forming interconnect lines, protruding features of the interconnect lines can be formed from insulating material. Consequently, polysilicon regions formed at the sides and top of the protruding features, which are not in electrical communication therewith, can be used to form separate interconnect lines. Such a protruding feature could also be an existing interconnect line, or a gate region, and could have thereon an insulating layer for electrically isolating the protruding feature from the region of polysilicon located on top of the protruding feature. Thus, the region of polysilicon situated on the protruding feature and the protruding feature can each form separate interconnect lines.
When forming interconnect lines or other such conducting shaped structures, the polysilicon region, once formed on a horizontal surface, can be converted to a refractory metal silicide to increase the conductivity thereof. In so doing, a layer of refractory metal such as titanium is deposited over the region of polysilicon, typically as a blanket layer. Thereafter, a heating treatment is conducted to react the exposed region of polysilicon with the refractory metal. The portions of the unreacted refractory metal can then be removed with a suitable etching process which etches the refractory metal selective to a silicide of the refractory metal. Refractory metal silicide is left over the exposed horizontal surface in the location where the region of polysilicon was located.
The interconnect lines and halo mask implant are each formed in a simple and efficient manner that is compatible with current process flows. The interconnect lines can be formed close together with high density, and the halo implant mask can be formed accurately and with appropriately sized openings which are useful in forming highly miniaturized transistors.
An eighteenth method of the present invention uses the etching process which is selective to implanted silicon-containing material of the first method. The eighteenth method forms a narrow interconnect line that is integrally connected to a region of greater width for electrically connecting the interconnect line to a larger structure. The narrow interconnect line can be formed with a sub-photolithography resolution width.
The eighteenth method initially involves providing a layer of silicon-containing material, which by way of example in the embodiment to be discussed is a polysilicon layer on a semiconductor substrate. The polysilicon layer is preferably formed from intrinsic polysilicon. Once the polysilicon layer is deposited, a masking substrate is applied and is patterned with an opening through which a selected region of the polysilicon layer will be implanted with ions. The selected region is used for connecting the interconnect line, once formed, with a structure of greater width than the interconnect line.
After the masking substrate is applied, a first ion implantation process is conducted in which the selected region is implanted with ions of a selected type chosen in accordance with an etching process which is selective to implanted silicon-containing material, as was discussed above for the first embodiment. The masking substrate is then removed and a second masking substrate is applied over the polysilicon layer and is patterned to have a selected surface shape, the outer periphery of which coincides with the desired location of the interconnect line. A dry etching process or equivalent material removal process is then conducted to reduce the polysilicon layer to a block of polysilicon having anisotropically etched sidewalls and a perimeter of the selected surface shape. The selected region is preferably located proximal to the perimeter of the block of polysilicon.
While the second masking substrate is in place, ions are implanted with a second ion implantation process into one or more laterally extending surfaces of the block of polysilicon. The ions are of a type that is selected in accordance with an etching process which is selective to implanted silicon-containing material as discussed for the first embodiment. The ions of the second ion implantation operation can be of the same type as the ions of the first ion implantation process, or can be of a different type. The ions of the second implantation process are implanted with an angle and energy selected to implant ions into laterally extending surfaces of the block of polysilicon to a selected depth. The selected depth corresponds to the thickness of the completed interconnect line. The angle of implantation is conducted essentially in the manner discussed above for the first and sixth methods.
After ion implantation is conducted, the etching process which is selective to implanted silicon-containing material is conducted substantially as described above in the discussion of the first method. The result is that unimplanted polysilicon of the block of polysilicon is etched away and implanted polysilicon is left remaining. The implanted regions of the one or more sidewalls thus remains, as does the selected region. The selected region of the polysilicon layer forms a contact pad and is integrally connected with the interconnect line. Of course, more than one contact pad can be formed on the interconnect line, and more than one interconnect line can be formed.
The entire perimeter of the block of polysilicon can be implanted so as to divide the block of polysilicon into two or more separate interconnect lines that are separated by breaks formed in the interconnect lines. In one embodiment, the breaks are formed using sacrificial spacer blocks close to the outer perimeter of the block of polysilicon. The sacrificial spacer blocks are formed prior to the second ion implantation operation, preferably during the patterning and formation of the block of polysilicon. The sacrificial spacer blocks absorb the implanted ions and block the implanted ions from implanting a segment of the sidewall of the block of polysilicon. Consequently, an opening is formed at the location of the segment that was not implanted, causing therein a break in the resulting interconnect line. Alternatively, the opening could be formed with a separate masking and etching procedure that is conducted after the interconnect line has been formed.
The interconnect line formed by the eighteenth method has a shape determined by the angle of implantation and the implantation energy, rather than by photolithography, and consequently can have a width that is smaller than that which can be provided by conventional photolithography processes. The interconnect line of the eighteenth method is also formed with an integral structure of greater width than the interconnect line for connecting the interconnect line to a larger structure. Consequently, the interconnect line can be highly miniaturized, while maintaining the flexibility of being able to connect easily to other semiconductor devices or features of semiconductor devices thereof. Additionally, the narrower interconnect line can be used as a gate region and when so used will have a short channel length. The short channel length allows for a lower threshold voltage of the MOS transistor and consequently a higher speed.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.